Alliance Memory DDR3 Synchronous DRAM

Alliance Memory DDR3 Synchronous DRAM (SDRAM) achieves high-speed double-data-rate transfer rates of up to 1600Mb/sec/pin for general applications. The chip is designed to comply with all key DDR3 DRAM key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK# falling). All I/Os are synchronized with differential DQS pairs in a source synchronous fashion. These devices operate with a single 1.5V ± 0.075V power supply and are available in BGA packages.

Features

  • JEDEC standard compliant
  • Power supplies: VDD & VDDQ = +1.5V ± 0.075V
  • Commercial operating temperature (0 ~ 95°C)
  • Industrial operating temperature (-40° ~ 105°C)
  • Supports JEDEC clock jitter specification
  • Fully synchronous operation
  • Fast clock rate 800MHz
  • Differential clock inputs, CK & CK#
  • Bidirectional differential data strobe - DQS & DQS#
  • 8 internal banks for concurrent operation
  • 8n-bit prefetch architecture
  • Internal pipeline architecture
  • Precharge & active power down
  • Programmable mode & extended mode registers
  • Additive Latency (AL): 0, CL-1, CL-2
  • Programmable Burst lengths: 4 and 8
  • Burst Type: Sequential / Interleave
  • Output driver impedance control
  • 8192 refresh cycles / 64ms
  • Write leveling
  • OCD calibration
  • Dynamic ODT (Rtt_Nom & Rtt_WR)
  • RoHS compliant (Lead-free and Halogen-free)
  • Auto-refresh and self-refresh
  • TFBGA package (78 Ball and 96 Ball )
  • All parts are RoHS compliant
公開: 2014-02-25 | 更新済み: 2021-09-02