ISSI IS25LP0 & IS25WP0 Serial NOR Flash
ISSI IS25LP0 and IS25WP0 Serial NOR Flash deliver a versatile storage solution with high flexibility and performance in a simplified pin count package. The IS25LP0 and IS25WP0 Flash are designed for systems that require limited space, a low pin count, and low power consumption.
The ISSI IS25LP0 and IS25WP0 Serial NOR Flash are utilized through a 4-wire SPI Interface consisting of a Serial Data Input (SI), Serial Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins, which also can be configured to serve as multi-I/O. The IS25LP0 and IS25WP0 support Dual and Quad I/O and standard, Dual Output, and Quad Output SPI.
The device's memory array is organized into programmable pages of 256 bytes and supports page program mode, where 1 to 256 bytes of data are programmed in a single command.
Specifications
- Industry Standard Serial Interface
- IS25LP040E: 4Mbit/512Kbyte
- IS25WP040E: 4Mbit/512Kbyte
- IS25LP020E: 2Mbit/256Kbyte
- IS25WP020E: 2Mbit/256Kbyte
- IS25LP010E: 1Mbit/128Kbyte
- IS25WP010E: 1Mbit/128Kbyte
- IS25LP512E: 512Kbit/64Kbyte
- IS25WP512E: 512Kbit/64Kbyte
- IS25LP025E: 256Kbit/32Kbyte
- IS25WP025E: 256Kbit/32Kbyte
- 256 bytes per Programmable Page
- Supports standard SPI, Multi-I/O SPI, and QPI
- Supports Serial Flash Discoverable Parameters (SFDP)
- Flexible and efficient memory architecture
- Chip erase with uniform sector/block erase (4/32/64Kbyte)
- Program 1 to 256bytes per page
- Program/Erase suspend and resume
- Soft RESET and In-Band RESET
- Efficient read and program modes
- XIP Read operation; dual I/O and quad IO read with AX mode
- Continuous Read and Wrap Burst Read (8/16/32/64-Byte)
- Program operation during erase suspend mode
Block Diagram
Connection Diagram among SPI Master & SPI Slaves
公開: 2021-12-20
| 更新済み: 2024-03-05