Skyworks Solutions Inc. SKY535x Differential Clock Buffers

Skyworks Solutions Inc. SKY535x Differential Clock Buffers are a series of fanout buffers ideal for high-frequency, low-jitter clock distribution. The devices offer universal-level format translation and ultra-low additive RMS phase jitter over various conditions, incorporating frequency and input clock slew rate. Separate core and output voltages are featured, supporting voltage down to 1.8V to enable additional power savings. Built-in LDOs provide high PSRR performance and decrease the requirement for external components, simplifying low-jitter clock distribution in noisy environments.

The SKY535x0 differential clock buffers feature a selectable input clock using a 3:1 input mux, a single-ended reference output, and either 10, 8, or 4 differential outputs in two banks. Each of which can be selected as LVPECL, LVDS, HCSL, or tristate. The SKY535x1 differential clock buffers offer a selectable input clock using a 3:1 input mux, a single-ended reference output, and up to 20, 16, or 8 in-phase LVCMOS outputs in two banks.

The SKY53512/82/42 and SKY53513/83/43 differential clock buffers feature an I2C interface for selecting the input source to each of the two output banks. The I2C interface can also be used to select the output format for each of the two output banks, as well as the output state for each clock output. The devices support 10, 8, or 4 outputs in two banks, each of which can be set to LVPECL, LVDS, HCSL, 800mV LVDS, or complementary LVCMOS.

Each output bank has its dedicated 1.8V, 2.5V, or 3.3V output voltage supply. The series of fanout buffers can be paired with the Skyworks NetSync™ family of network synchronizer clocks, jitter attenuators, and clock generators and oscillators to deliver ultra-low-jitter clock tree solutions.

Evaluation Board Kits

The SKY53511‑A‑EVB, SKY53512‑A‑EVB, and SKY53513‑A‑EVB evaluation board kits allow users to quickly evaluate the performance of SKY53511/81/41, SKY53512/82/42, and SKY53513/83/43 ultra‑low additive jitter fanout buffers, respectively. The jumpers can be easily configured with no external software required, and SMA connections make it easy to connect to test equipment.

Features

  • Ultra‑low additive jitter (156.25MHz LVPECL):
    • 35fs RMS typical (12kHz to 20MHz)
    • 29fs RMS typical (12kHz to 20MHz, 4MHz HPF)
    • 47fs RMS max (12kHz to 20MHz)
    • 39fs RMS max (12kHz to 20MHz, 4MHz HPF)
  • 3:1 input multiplexer:
    • Two any‑format universal inputs supporting LVPECL, LVDS, S‑LVDS, HCSL, CML, SSTL, HSTL, and sine wave inputs
    • One crystal input (also accepts a single‑ended square wave or sine wave clock)
  • Frequency range:
    • DC to 3.1GHz LVPECL
    • DC to 3GHz LVDS
    • DC to 800MHz HCSL
    • DC to 250MHz LVCMOS
  • PCIe Gen1/2/3/4/5/6/7 compliant
  • 1.8V, 2.5V, or 3.3V low‑power operation (VDD/VDDO)
  • LVCMOS REFOUT output with synchronous enable/disable
  • Temperature range:
    • -40°C to 95°C ambient temperature
    • 105°C maximum board temperature
  • Packages:
    • 48-pin, 7mm x 7mm QFN (SKY53510/11 and SKY53512/13)
    • 40-pin, 6mm x 6mm QFN (SKY53580/81 and SKY53582/83)
    • 32-pin, 5mm x 5mm QFN (SKY53540/41 and SKY53542/43)

Applications

  • SKY535x2/x3:
    • 56G/112G/224G PAM4 SerDes clocking
    • 400G/800G/1.6T switches and routers
    • 5G/6G wireless infrastructure
    • Data center switches
公開: 2025-01-21 | 更新済み: 2026-04-03