Zentel DDR2 SDRAM
Zentel DDR2 SDRAM features a double-data-rate architecture with two data transfers per clock cycle. The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture. A bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver. DQS is edge-aligned with data for READs; center-aligned with data for WRITEs Differential clock inputs (CK and /CK). The DLL aligns DQ and DQS transitions with CK transitions.
Features
- Double-data-rate architecture; two data transfers per clock cycle
- The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
- Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver
- DQS is edge-aligned with data for READs; center-aligned with data for WRITEs
- Differential clock inputs (CK and /CK)
- DLL aligns DQ and DQS transitions with CK transitions
- Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
- Data mask (DM) for write data
- Posted /CAS by programmable additive latency for better command and data bus efficiency
- On-Die-Termination for better signal quality
- /DQS can be disabled for single-ended Data Strobe operation
- Off-Chip Driver (OCD) impedance adjustment is not supported
View Results ( 10 ) Page
| 部品番号 | データシート | 説明 |
|---|---|---|
| A3R12E40DBF-8E |  |
DRAM DDR2 512Mb, 32Mx16, 800 at CL5, 1.8V, FBGA-84 |
| A3R12E30DBF-8E | |
DRAM DDR2 512Mb, 64Mx8, 800 at CL5, 1.8V, FBGA-60 |
| A3R1GE30JBF-8E | |
DRAM DDR2 1Gb, 128Mx8, 800 at CL5, 1.8V, FBGA-60 |
| A3R12E40DBF-8EA | |
DRAM DDR2 512Mb, 32Mx16, 800 at CL5, 1.8V, FBGA-84, 105C |
| A3R12E40DBF-8EI | |
DRAM DDR2 512Mb, 32Mx16, 800 at CL5, 1.8V, FBGA-84, Ind. Temp. |
| A3R12E40DBF-AH | |
DRAM DDR2 512Mb, 32Mx16, 1066 at CL7, 1.8V, FBGA-84 |
| A3R1GE40JBF-8E | |
DRAM DDR2 1Gb, 64Mx16, 800 at CL5, 1.8V, FBGA-84 |
| A3R1GE40JBF-8EA | |
DRAM DDR2 1Gb, 64Mx16, 800 at CL5, 1.8V, FBGA-84, 105C |
| A3R1GE40JBF-8EI | |
DRAM DDR2 1Gb, 64Mx16, 800 at CL5, 1.8V, FBGA-84, Ind. Temp. |
| A3R1GE40JBF-AH | |
DRAM DDR2 1Gb, 64Mx16, 1066 at CL7, 1.8V, FBGA-84 |
公開: 2021-06-28
| 更新済み: 2025-09-26